(a) Field of the Invention
The present invention relates to a signal converting circuit and a display apparatus having the signal converting circuit. More particularly, the present invention relates to a signal converting circuit to drive a shift register and a display apparatus having the signal converting circuit.
(b) Description of the Related Art
In order to decrease a manufacturing cost of a display apparatus and to manufacture the display apparatus having a narrow bezel, a gate driving circuit or a data driving circuit is integrated on a display panel, for example, such as a liquid crystal display (LCD) panel, a plasma display panel (PDP), an organic light emitting display (OLED) panel, etc. A scan driving circuit having amorphous silicon thin film transistors (a-Si TFTs) may have a simplified structure so that the gate driving circuit or the data driving circuit is integrated on the LCD panel. The scan driving circuit having the a-Si TFTs may have a lower manufacturing cost than the scan driving circuit having poly-silicon TFTs.
A conventional scan driving circuit includes a shift register. The scan driving circuit outputs a gate pulse to activate a scan line of an LCD panel. A unit stage of the shift register includes an S-R latch and an AND gate.
The S-R latch is activated by a first input signal that is an output signal of a previous stage, and the S-R latch is deactivated by a second input signal that is an output signal of a next stage. When the S-R latch is activated and a first clock signal is in a high state, the AND gate generates the gate pulse. The gate pulse may be a scan signal.
The first clock signal and a second clock signal having an opposite phase to the first clock signal are applied to the unit stage of the shift register to activate scan lines.
The unit stage of the shift register includes a buffering circuit, a charging circuit, a driving circuit and a discharging circuit. The shift register outputs the gate signal based on a scan start signal or the output signal of the previous stage.
The buffering circuit has a first transistor including a first drain electrode, a first gate electrode and a first source electrode. The first drain electrode is electrically connected to the first gate electrode to receive the first input signal. The first source electrode is electrically connected to a first capacitor electrode of the charging circuit that includes a capacitor. The first capacitor electrode of the capacitor is electrically connected to the first source electrode of the first transistor and the discharging circuit. A second capacitor electrode of the capacitor is electrically connected to the driving circuit.
The driving circuit has a second transistor and a third transistor. The second transistor includes a second drain electrode, a second gate electrode and a second source electrode. The second drain electrode is electrically connected to a clock terminal. The second gate electrode is electrically connected to the first capacitor electrode of the capacitor of the charging circuit through a first node. The second source electrode is electrically connected to the second capacitor electrode of the capacitor and the output terminal. The third transistor includes a third drain electrode, a third source electrode and a third gate electrode. The third drain electrode is electrically connected to the second source electrode of the second transistor and the second capacitor electrode of the capacitor. The first voltage is applied to the third source electrode. The first clock signal or the second clock signal that has the opposite phase to the first clock signal is applied to the clock terminal.
The discharging circuit has a fourth transistor that includes a fourth drain electrode, a fourth gate electrode and a fourth source electrode. The fourth drain electrode is electrically connected to the first capacitor electrode of the capacitor. The fourth gate electrode is electrically connected to the third gate electrode of the third transistor to receive the second input signal. The first voltage is applied to the fourth source electrode.
When the first input signal is in the high state, an electric charge is stored in the capacitor. When the second input signal is in the high state, the electric charge that is stored in the capacitor is discharged to perform an S-R latch operation.
When the electric charge is stored in the capacitor, the first clock signal or the second clock signal that is applied to the clock terminal is applied to the output terminal through the second transistor that is turned on by the stored electric charge. When the first clock signal is or the second clock signal is applied to the output terminal that is electrically connected to a scan line of the LCD panel, amorphous-silicon (a-Si) TFTs that are electrically connected to the scan line are turned on. Each of the a-Si TFTs functions as a switching transistor. The second transistor is turned on by the second input signal so that the output terminal is pulled down at the first voltage, thereby performing an AND gate operation.
A driving voltage for turning on each of the a-Si TFTs that are electrically connected to the scan line in a display region may be higher than a driving voltage for turning on each of the poly silicon TFTs. In addition, the first voltage for turning off each of the a-Si TFTs is lower than a turn-off voltage for turning off each of the poly silicon TFTs. That is, a voltage range for driving the shift register having the a-Si TFTs is wider than a voltage range for driving the shift register having the poly silicon TFTs.